1. Field of the Invention
The present invention relates to a static random access memory device, and more particularly, to a highly integrated structure of a memory cell in a static random access memory which includes load resistors of high resistance.
2. Description of the Background Art
The outstanding development of information equipment such as computers has made higher requirements necessary for the semiconductor memory devices used in the equipment. Particularly, the demand for semiconductor memory devices with large-scale storage capacity has increased and technological research and development directed to higher speed and more highly integrated devices has been promoted intensively.
An example of such a semiconductor memory device is a Static Random Access Memory (referred to as SRAM hereinafter). In the SRAM, a memory cell which stores memory information includes four to six MOS (Metal Oxide Semiconductor) transistors. A conventional type of memory cell in which MOS transistors are interconnected to constitute a flip-flop circuit is generally known. The SRAM has also been highly integrated to have an enhanced storage capacity, which has resulted in a load resistor-type SRAM suited for integration.
FIG. 4 illustrates an equivalent circuit diagram of a memory cell in a SRAM using load resistors. In reference to the diagram, a memory cell includes four MOS transistors and two load resistors. The four MOS transistors include two drive transistors 2a and 2b and two transfer transistors 3a and 3b. The drive transistor 2a has a gate electrode connected to a drain electrode of the drive transistor 2b and a drain electrode connected to a gate electrode of the transistor 2b. Furthermore, two load resistors 4a and 4b are connected to the drain electrodes of the transistors 2a and 2b, respectively. The gate electrodes of the transfer transistors 3a and 3b are connected to a word line 5. One source/drain electrode of the transfer transistor 3a is connected to a bit line 6a and one source/drain electrode of the transfer transistor 3b is connected to a bit line 6b. Meanwhile, the other ends of the load resistors 4a and 4b are connected to the supply voltage Vcc.
A sectional structure of the above mentioned memory cell will be described next. FIGS. 5A to 5E are sectional views of the memory cell 1 in the regular sequence of a manufacturing process, wherein a drive transistor 2a, a load resistor 4a and so forth are typically illustrated.
First, as illustrated in FIG. 5A, a field oxide film 8 is formed in a predetermined region of a surface of a silicon substrate 7 by the selective oxidation method. A gate oxide film 9 is then formed on a surface of the silicon substrate 7 by a thermal oxidation method. Furthermore, after impurities for adjusting the threshold voltage are ion-implanted into a surface of the silicon substrate 7, a polysilicon layer 10 is deposited by a CVD (Chemical Vapor Deposition). Subsequently, a high melting metal film 11, such as tungsten (W), is deposited thereon by CVD.
Secondly, as illustrated in FIG. 5B, the high melting metal film 11 and the polysilicon layer 10 are patterned to exhibit a predetermined configuration by photolithography and etching steps. A gate electrode 12 of the drive transistor 2a is formed through this process. Source and drain regions 13 are then formed by ion implantation of impurities in surface regions of the silicon substrate 7 using the gate electrode 12 as a mask. Thereafter, an oxide film 14 is deposited on the surface of the silicon substrate 7 by CVD.
Furthermore, as illustrated in FIG. 5C, a contact hole 15 is formed in the oxide film 14 by photolithography technique and etching is performed to reach the impurity region 13. A second polysilicon layer 16 is in turn deposted on an inner surface of the contact hole 15 and the remaining surfaces by the CVD. In addition, a very small amount of impurities is introduced into the second polysilicon layer 16 by ion implantation. The second polysilicon layer 16 becomes a conductive layer with a high resistance through this process.
Next, as illustrated in FIG. 5D, impurities having a high density are introduced by ion implantation into an area of the second polysilicon layer 16 deposited on the impurity region 13 so that the resistance of that area will be reduced. Thus, an interconnection region 17 is formed in the area of the second polysilicon layer 16 which includes impurities of high density. Meanwhile, a remaining area of the second polysilicon layer 16 has a very small amount of impurities introduced by ion implantation in order to constitute a load resistor 4a.
As illustrated in FIG. 5E, the second polysilicon layer 16 is then patterned to have an interconnection layer 17 and a load resistor 4a of a predetermined configuration by photolithography and etching steps. A silicon oxide film 18 is in turn deposited by CVD, and a BPSG (Boro Phospho Silicate Glass) film 19 is further deposited by CVD&gt; A contact hole 20 is then formed in the BPSG film 19 and the silicon oxide film 18 to reach the impurity region 13 Thereafter, an interconnection layer 21, such as aluminum, is deposited in this contact hole 20. Finally, the entire surface is coated with a passivation film (not shown) which completes the manufacturing process of the memory cells.
In the foregoing description, a conventional SRAM is formed with load resistors having a polysilicon layer of high resistance. In addition, the illustrated structure is characterized by forming a so-called double layer polysilicon structure having a polysilicon layer which forms a gate electrode 12 with a polysilicon layer which forms a load resistor stacked thereon.
In order to enhance the high speed operation characteristics of a highly integrated SRAM, it becomes increasingly necessary to reduce the interconnection resistance thereof. Additionally, memory cells of a SRAM as manufactured according to the above mentioned manufacturing process need at least three photolithography processes to form load resistors during the manufacturing process. This process includes complicated processing steps, such as a pattern mask formation process, a mask alignment process, or an exposure and development process. Therefore, as the number of photolithography processes is increased, the entire manufacturing process of memory cells becomes more and more complicated. In addition, the manufacturing process of a load resistor 4a includes patterning a polysilicon layer and ions selectively implanting into the polysilicon layer with different densities. Moreover, this process is performed as an independent process to form a load resistor. Accordingly, the total number of processes included in the manufacturing process is increased. The SRAM requiring such complicated manufacturing processes has encountered difficulties, especially in the case where the SRAM is formed on one chip and combined with a CPU (Central Processing Unit) and other memories in an ASIC (Applied Specification Integrated Circuit).